Non-Contact testing of Silicon Chips

Description:

This technology reduces the cost of testing electronic chips while enabling tests on high density chips and systems-on-a-chip, which are increasing in importance as portable devices increase in the market. The non-contact coupling of the probes eliminates many of the problems associated with state of the art tests. Testing is a major cost in the microelectronics industry, and represents a major opportunity for reducing chip costs, especially as more powerful chips move into mobile devices.

Description: Optical structures such as optical gratings and detectors implemented as surface plasmon polariton structures are used in order to allow non-contact optical coupling of test cards to chips. The technology replaces test heads that use many contact pins and high pressure. The chips being tested only require the addition of a few optical structures. This will bring enormous benefits to the microelectronics industry, which is expected to spend $ 4 billion on probe cards alone by 2017. It will bring the following benefits to this market:

  • Durability as it does not wear or see reduced performance after 200 touchdowns as seen with contact systems

  • Low maintenance with few contact pins to calibrate, clean, maintain, and replace

  • Higher yields and reduced damage over high contact systems that use forces up to 1500 Kg.

  • Lower systems and maintenance costs as high forces require costly servos

  • Scaleable to smaller feature sizes emerging in the market

  • High volume manufacturing of test probes possible to meet expected demand

Patent Information:
For Information, Contact:
Jaipreet Bindra
University of Ottawa
jbindra2@uottawa.ca
Inventors:
Pierre Berini
Chengkun Chen
Keywords: